This invention relates to a logic arithmetic circuit which performs full-addition of binary numbers, and more particularly, to a reduction in the number of elements required to form a full-adder circuit.
In response to operand input signals A and B, and a carry signal Cin from the lower-order digit, a well-known binary full-adder circuit produces an operated output signal S and a carry signal Cout to a higher-order digit.
FIG. 1 shows a circuit diagram of a conventional full-adder circuit. This circuit comprises exclusive OR gates 4.sub.1 and 4.sub.2 including NOR gate 1, AND gate 2, and NOR gate 3. Operand input signals A and B are input to OR gate 4.sub.1. The output from exclusive OR gate 4.sub.1 and carry signal Cin from a lower-order digit are supplied to exclusive OR gate 4.sub.2. A signal from exclusive OR gate 4.sub.2 is output as an operated output signal.
The circuit including AND gates 5 and 6, NOR gate 7, and inverters 8 and 9, is a carry circuit. This carry circuit outputs carry signal Cout to a higher-order digit, according to carry signal Cin from a lower-order digit and operand input signals A and B.
FIG. 2 shows a circuit diagram of another conventional full-adder circuit. In this full-adder circuit, a so-called Manchester type carry circuit is used as its carry circuit. More specifically, this type of carry circuit comprises N-channel MOS transistors 10.sub.1 and 10.sub.2, which are connected in series between the high voltage V.sub.DD and carry signal Cin from a lower-order digit. In this circuit, MOS transistors 10.sub.1 and 10.sub.2 are controlled according to signals A, B, and Cin, so that the logic level of carry signal Cout to a higher-order digit is controlled. The junction of transistors 10.sub.1 and 10.sub.2 provides the output terminal for carry signal Cout to a higher-order digit.
In a conventional circuit thus arranged, operated output signal S and carry signal Cout can be expressed as follows, using operand input signals A and B, and carry signal Cin: EQU S=A.multidot.B.multidot.Cin+A.multidot.B.multidot.Cin+A.multidot.B.multidot .Cin+A.multidot.B.multidot.Cin (1) EQU Cout=A.multidot.B+A.multidot.B.multidot.Cin+A.multidot.B.multidot.Cin (2)
These formulas (1) and (2) are tabulated into the truth table shown in FIG. 3.
The MOS type integrated circuit (abbreviated MOS-IC), now widely used, has been continuously improved, and this has resulted in a remarkable increase in its integration density. The requirements for a MOS-IC circuit design are follows:
The first requirement is how to realize a system having a logical function, and having the smallest possible number of elements, such as transistors.
The second requirement is how to realize high speed operation and, at the same time low power consumption.
Of these two requirements, the latter, viz., high speed operation and low power consumption, has been realized to a certain degree, by arranging the circuit with CMOSs, and making them dynamic-operated.
As for the former, viz., reduction of the number of elements, no effective way to achieve this has been discovered so far. To give some examples, if a conventional circuit is arranged as shown in FIGS. 1 and 2, sixteen P-channel MOS transistors and sixteen N-channel MOS transistors are required for the FIG. 1 circuit, that is, the FIG. 1 circuit requires a total of thirty-two elements. For the FIG. 2 circuit, fourteen P-channel MOS transistors and sixteen N-channel MOS transistors are required. The number of elements required for this circuit is, therefore, thirty in total. Thus, conventional circuits require numerous elements.